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data sheet version 1.1 1 1999-08-04 5-v low-drop voltage regulator tle 4275 preliminary data features ? output voltage 5 v 2% ? very low current consumption ? power-on and undervoltage reset ? reset low down to v q = 1 v ? very low-drop voltage ? short-circuit-proof ? reverse polarity proof ? suitable for use in automotive electronics t new type functional description the tle 4275 is a monolithic integrated low-drop voltage regulator in a 5 pin to-package. an input voltage up to 45 v is regulated to v q = 5.0 v. the ic is able to drive loads up to 450 ma and is short-circuit proof. at over temperature the tle 4275 is disabled by the incorporated temperature protection. a reset signal is generated for an output voltage v q of typ. 4.65 v. the delay time can be programmed by the external delay capacitor. type ordering code package t tle 4275 d q67006-a9354 p-to252-5-1 (smd) t tle 4275 g q67006-a9343 p-to263-5-1 (smd) t tle 4275 q67000-a9342 p-to220-5-11 t tle 4275 s q67000-a9442 p-to220-5-12 p-to252-5-1 p-to263-5-1 p-to220-5-11 p-to220-5-12
tle 4275 data sheet version 1.1 2 1999-08-04 dimensioning information on external components the input capacitor c i is necessary for compensating line influences. using a resistor of approx. 1 w in series with c i , the oscillating of input inductivity and input capacitance can be damped. the output capacitor c q is necessary for the stability of the regulation circuit. stability is guaranteed at values c q 3 22 m f and an esr of 5 w within the operating temperature range. circuit description the control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. saturation control as a function of the load current prevents any oversaturation of the power element. the ic also incorporates a number of internal circuits for protection against: ? overload ? over-temperature ? reverse polarity
data sheet version 1.1 3 1999-08-04 tle 4275 pin configuration (top view) figure 1 pin definitions and functions pin no. symbol function 1 i input ; block to ground directly at the ic with a ceramic capacitor. 2rq reset output ; open collector output 3 gnd ground ; pin 3 internally connected to heatsink 4d reset delay ; connected capacitor to gnd for setting delay time 5q output ; block to ground with a 3 22 m f capacitor, esr < 5 w at 10 khz. aep02580 15 ro i dq gnd aep02756 gnd i rq q d p-to252-5-1 (d-pak) p-to263-5-1 (smd) gnd rq i iep02528 d q iep02527 i rq gnd d q p-to220-5-11 p-to220-5-12
tle 4275 data sheet version 1.1 4 1999-08-04 figure 2 block diagram i aeb02425 gnd q temperature sensor reference bandgap buffer saturation control and protection circuit generator reset d rq
data sheet version 1.1 5 1999-08-04 tle 4275 note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. absolute maximum ratings t j = C 40 to 150 c parameter symbol limit values unit test condition min. max. voltage regulator input voltage v i C42 45 v C current i i CC C internally limited output voltage v q C 1.0 16 v C current i q C C C internally limited reset output voltage v ro C 0.3 25 v C current i ro C 5 5 ma C reset delay voltage v d C 0.3 7 v C current i d C 2 2 ma C temperature junction temperature t j C 150 cC storage temperature t stg C 50 150 cC
tle 4275 data sheet version 1.1 6 1999-08-04 operating range parameter symbol limit values unit remarks min. max. input voltage v i 5.5 42 v C junction temperature t j C 40 150 cC thermal resistance junction case r thjc C 4 k/w C junction ambient r thja C 70 k/w to263 junction ambient r thja C 70 k/w to252 1) junction ambient r thja C 65 k/w to220 1) soldered in, minimal footprint characteristics v i = 13.5 v; C 40 c< t j < 150 c (unless otherwise specified) parameter symbol limit values unit measuring condition min. typ. max. output output voltage v q 4.9 5.0 5.1 v 5ma< i q < 400 ma 6v< v i <40v output current limitation 1) i q 450 700 C ma C current consumption; i q = i i C i q i q C 150 200 m a i q = 1 ma; t j =25 c current consumption; i q = i i C i q i q C 150 220 m a i q = 1 ma; t j 85 c current consumption; i q = i i C i q i q i q C5 12 10 22 ma ma i q = 250 ma i q = 400 ma drop voltage 1) v dr C 250 500 mv i q = 300 ma v dr = v i C v q load regulation d v q C1530mv i q = 5 ma to 400 ma line regulation d v q C 15 5 15 mv d v l = 8 v to 32 v i q =5ma
data sheet version 1.1 7 1999-08-04 tle 4275 figure 3 power supply ripple rejection psrr C60Cdb f r = 100 hz; v r = 0.5 vpp temperature output voltage drift C 0.5 C mv/ k C reset timing d and output rq reset switching threshold v rt 4.5 4.65 4.8 v C reset output low voltage v rql C 0.2 0.4 v r ext 3 5k w ; v q > 1 v reset output leakage current i rqh C02 m a v rqh > 4.5 v reset charging current i d 369 m a v d = 1 v upper timing threshold v du 1.5 1.8 2.2 v C lower timing threshold v dl 0.2 0.4 0.7 v C reset delay time t d 10 16 22 ms c d = 47 nf reset reaction time t rr C 0.5 2 m s c d = 47 nf 1) measured when the output voltage v q has dropped 100 mv from the nominal value obtained at v i = 13.5 v. characteristics (contd) v i = 13.5 v; C 40 c< t j < 150 c (unless otherwise specified) parameter symbol limit values unit measuring condition min. typ. max. dv q dt ----------- 1000 f 47 nf 4 i i i v q rq i q rq i c i v q rq v c q aes02472 i gnd d i c d gnd m 2 c i 1 1 d dis i 3 2 5 22 f m d v 100 nf 5 k ext r w
tle 4275 data sheet version 1.1 8 1999-08-04 test circuit figure 4 reset timing aed01542 thermal t d power-on-reset voltage dip secondary overload at output spike v st v i v d v ro d i = v d dt v q rt v t rr < rr t v dt at input undervoltage shutdown c d
data sheet version 1.1 9 1999-08-04 tle 4275 output voltage v q versus temperature t j output current i q versus temperature t j output voltage v q versus input voltage v i output current i q versus input voltage v i 4.90 4.80 4.70 40 -40 0 4.60 5.00 v 5.20 5.10 q 160 c 80 120 t j aed01928 v i = 13.5 v v 600 400 200 40 -40 0 0 800 ma 1200 1000 q i 160 c 80 120 t j aed01930 r 6 4 2 0 4 0 2 8 12 10 q v v 10 v 68 v i aed01929 = 25 l w 0.6 0.4 0.2 20 010 0 0.8 a 1.2 1.0 q i = 25 c t j 50 v 30 40 v i aed01931 = 125 c t j
data sheet version 1.1 10 1999-08-04 tle 4275 current consumption i q versus output current i q current consumption i q versus output current i q drop voltage v dr versus output current i q charge current i d versus temperature t j 0 0 20 120 60 40 i q ma aed01932 80 ma 1 2 3 4 5 6 q i v i = 13.5 v 300 40 30 100 0 200 0 10 20 80 60 70 50 ma q i v = 13.5 v i ma 400 600 i q aed01933 400 200 300 100 200 0 400 0 800 600 700 500 dr v mv ma 600 1000 i q aed01935 t = 125 c j t =25 j c 4 2 3 1 0 -40 40 0 8 6 7 5 d i a c 120 80 160 t j aed01936 d i v i = 13.5 v = 1 v d v m
data sheet version 1.1 11 1999-08-04 tle 4275 delay switching threshold v du versus temperature t j 2.0 1.0 1.5 0.5 0 -40 40 0 4.0 3.0 3.5 2.5 dt v v c 120 80 160 t j aed01937 i v = 13.5 v du v
tle 4275 data sheet version 1.1 12 1999-08-04 package outlines gpt09161 5.4 0.1 -0.10 6.5 +0.15 a 0.5 9.9 6.22 -0.2 1 0.1 0.15 0.8 0.15 max 0.1 per side 5x0.6 1.14 4.56 +0.08 -0.04 0.9 2.3 -0.10 +0.05 b 0.51 min 0.1 1 +0.08 -0.04 0.5 0...0.15 b a 0.25 m 0.1 all metal surfaces tin plated, except area of cut. (4.17) p-to252-5-1 (d-pak) (plastic transistor single outline) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
data sheet version 1.1 13 1999-08-04 tle 4275 a 8? max. b a 0.25 m 0.1 typical 9.8 0.15 0.2 10 8.5 1) 8 1) (15) 0.2 9.25 0.3 1 0...0.15 5x0.8 0.1 0.1 1.27 4.4 b 0.5 0.1 0.3 2.7 4.7 0.5 0.05 1) 0.1 all metal surfaces tin plated, except area of cut. 2.4 4x1.7 p-to263-5-1 (smd) (plastic transistor single outline) gpt09113 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
tle 4275 data sheet version 1.1 14 1999-08-04 gpt09064 a a 0.25 m typical 9.8 0.15 2.8 1) 15.65 0.3 13.4 0...0.15 1.7 0.8 0.1 0.1 1.27 4.4 9.25 0.2 0.05 1) all metal surfaces tin plated, except area of cut. c 0.2 17 0.3 8.5 1) 10 0.2 3.7 -0.15 c 2.4 0.5 0.1 0.3 8.6 10.2 0.3 0.4 3.9 0.4 8.4 3.7 0.3 p-to220-5-11 (plastic transistor single outline) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm
data sheet version 1.1 15 1999-08-04 tle 4275 gpt09065 a b a 0.25 m typical 9.8 0.15 2.8 1) 15.65 0.3 13.4 0...0.15 1.7 0.8 0.1 0.1 1.27 4.4 b 9.25 0.2 0.05 1) all metal surfaces tin plated, except area of cut. c 0.2 17 0.3 8.5 1) 10 0.2 3.7 -0.15 c 2.4 0.5 0.1 13 0.5 0.5 11 6x p-to220-5-12 (plastic transistor single outline) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm
tle 4275 data sheet version 1.1 16 1999-08-04 edition 1999-08-04 published by infineon technologies ag i. gr., st.-martin-strasse 53 d-81541 mnchen ? infineon technologies ag 1999 all rights reserved. attention please! the information herein is given to describe certain components and shall not be consid- ered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non- infringement, regarding circuits, descriptions and charts stated herein. infineon technologiesis an approved cecc manufacturer. information for further information on technology, deliv- ery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technolo- gies representatives worldwide (see ad- dress list). warnings due to technical requirements components may contain dangerous substances. for in- formation on the types in question please contact your nearest in?neon technologies of?ce. in?neon technologies components may only be used in life-support devices or systems with the express written approval of in?neon technologies, if a failure of such components can reasonably be expected to cause the fail- ure of that life-support device or system, or to affect the safety or effectiveness of that de- vice or system. life support devices or sys- tems are intended to be implanted in the hu- man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endan- gered.

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